IP Cores protection

One of the main issues raised by the design of systems based on reusable modules is the protection of the intellectual property of the modules (IP Cores) to be distributed. The solutions in this regard are usually based on the use of watermarking techniques, but focusing on the physical level. The line proposed by  DiTEC Research Group relays on improving protection levels without harming the area and/or performance of the system to be developed by means of incorporating secure digital signatures at the HDL description level. In this sense, work has been done in three directions:

  • Developing a system to incorporate hidden digital signatures ("watermarking") into high-level descriptions.
  • Developing a system to verify these signatures using side channels.
  • Developomg a semi-automatic tool to help the engineer to introduce signatures in designs.

These studies were carried out within the research project TEC2007-68074-C02-01 (IPP@HDL). The following table presents the publications with the proposals and results obtained.

IP Cores protection publications
Type of Publication Publication
Journal L. Parrilla, E. Castillo, E. Todorovich, A. García, D.P. Morales  and G.Botella. "Improvements for the applicability of power-watermarking to embedded IP cores protection: E-coreIPP". Digital Signal Processing, 44, 110-122. 2015.
Journal

E. Castillo, U. Meyer-Baese, A. García, L. Parrilla and A. Lloris, "IPP@HDL: Efficient Intellectual Property Protection Scheme for IP Cores", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 15, no. 15 , pp. 578-591. 2007
Conference U. Meyer-Bäse, E. Castillo, G. Botella, L. Parrilla and A. García, "Intellectual property protection (IPP) using obfuscation in C, VHDL, and verilog coding". In Independent Component Analyses, Wavelets, Neural Networks, Biosystems, and Nanoengineering IX (Vol. 8058, p. 80581F). June, 2011.
Conference J.J.L. Franco, E. Boemo, E., Castillo and L. Parrilla,  "Ring oscillators as thermal sensors in FPGAs: Experiments in low voltage," In 2010 VI Southern Programmable Logic Conference (SPL) , Marh 2010, pp. 133-137.
Conference L. Parrilla, E. Castillo, U. Meyer-Baese, A. García, D. González, E. Todorovich, and A. Lloris,  "Watermarking strategies for IP protection of micro-processor cores". In Independent Component Analyses, Wavelets, Neural Networks, Biosystems, and Nanoengineering VIII (Vol. 7703, p. 77030L). April 2010.
Conference E. Castillo, L. Parrilla, A. Garcia, U. Meyer-Baese, G. Botella,  and A. Lloris, "Automated signature insertion in combinational logic patterns for HDL IP core protection". In 2008 4th Southern Conference on Programmable Logic . March 2008, pp. 183-186.
Conference E. Castillo, L. Parrilla, A. García, U. Meyer-Baese and A. Lloris, "Automated Signature Hosting for Soft Core Protection", Proc. of XXII Conference on Design of Circuits and Integrated Systems DCIS'2007 (Seville, Nov. 21-23 2007), pp. 470-475.
Conference E. Castillo, L. Parrilla, A. García , U. Meyer-Baese and A. Lloris, "Intellectual Property Protection of HDL IP Cores through Automated Signature Hosting," Proc. of 17th International Conference on Field Programmable Logic and Applications FPL'2007 (Amsterdam, Aug. 27-29 2007), pp. 183-188
Conference E. Castillo, U. Meyer-Baese, A. García, L. Parrilla and A. Lloris, “Intellectual Property Protection of IP Cores Through High-Level Watermarking”, Proc. SPIE Independent Component Analyses, Wavelets, Unsupervised Nano-Biometric Sensors and Neural Networks (Orlando FL, 10-13 Apr. 2007), vol. 6576, pp. 657519-1-10
Conference E. Castillo, U. Meyer-Baese, A. García, L. Parrilla, D. P. Morales and A. Lloris, "Digital Signature Embedding Technique for IP Core Protection," Proc. of 3rd Southern Conference on Programmable Logic SPL'2007 (Mar del Plata, Feb. 26-28 2007), pp. 143-148
Conference E. Castillo, L. Parrilla, A. Garcia, A. Lloris, and U. Meyer-Baese. "Intellectual Property Protection of HDL IP Cores Through Automated Signature Hosting". In 2007 International Conference on Field Programmable Logic and Applications (pp. 183-188). August, 2007.
Conference

E. Castillo, L. Parrilla, A. Garcia, A LLoris and U. Meyer-Baese, "IPP watermarking technique for IP core protection on FPL devices". In 2006 International Conference on Field Programmable Logic and Applications. August 2006, pp. 1-6.
Conference L. Parrilla, E. Castillo, A. García and A. Lloris, A. "Intellectual property protection for RNS circuits on FPGAs". In International Conference on Field Programmable Logic and Applications. Springer, Berlin, Heidelberg, pp. 1139-1141. August 2004.